Definition of Reduction Instruction Set Computers

Reduced instruction set computer (RISC) is a computer that uses a central processing unit (CPU) that implements processor design principle of a simplified instruction. To date, RISC is the most efficient CPU architecture technology. This architecture is an evolution and alternative to computing complex instruction sets (CISC). With RISC, the basic concept is to have simple instructions that are not too many but run very fast to provide better performance.

Reduced Instruction Set Computing (RISC) was first conceived by John Cocke, a researcher from IBM in Yorktown, New York in 1974 when he proved that about 20% of instructions on a processor actually handled about 80% of the whole work. The first computer to use the RISC concept was the IBM PC / XT in the 1980s. The term RISC itself was first popularized by David Patterson, lecturer at the University of California at Berkely.

The important elements used in some general designs in RISC are as follows: a limited and simple set of instructions, a large number of general purpose registers or technology use, a compiler to optimize the use of registers, and an emphasis on optimizing instruction pipelines.

The most basic RISC feature is a processor with a small core logic logic which allows engineers to increase the set register and increase internal parallelism by using the following things:

Thread level parallelism: Increases the number of parallel threads executed by CPU

Instruction level parallelism: Increase the speed of CPU execution instructions

The words ” reduced instruction set ” or ” reduced instruction set ” often misinterpreted to refer to a reduced number of instructions. However, a collection of reduced instruction is not the problem, because some RISC processors work like a PowerPC, has a lot of instructions. At the other end of the spectrum, DEC PDP-8, CPU CISC, only has eight basic instructions. Reduction of instructions is actually meaningful that the amount of work done by each instruction decreases in terms of numbers cycle – at most only a single data memory cycle – compared to CISC CPU, where dozens of cycles are needed before completing all instructions. This results in faster processing.

RISC Pipelining

RISC pipeline processor operates the same way, although different stages in the pipeline. While different processors have different number of steps, they are basically variations of these five steps, which are used in the MIPS R3000 processor:

  1. Take instructions from memory (instruction fetch)

Cache Instructions on these machines have one cycle latency, which means that if the instruction is in the cache, it will be ready at the next clock cycle. 

During the Instruction Fetch phase, 32-bit instructions are taken from the cache. The Counter program, or PC, is a register that stores the current instruction address. It feeds into the PC predictor, which then sends the Counter Program (PC) to the Cache Instructions to read the current instructions. At the same time, the PC predictor predicts the address of the next instruction by adding 4 PCs (all instructions are 4 bytes long). This prediction is always wrong in the case of branches being taken, jumped, or excluded (see pending branches, below). The machine will use a more complicated and accurate algorithm (branch prediction and branch target prediction) to guess the address of the next instruction

2. Read the instruction and instruction decode

  • Not as previously microcoded engine, the first RISC machine does not have microcoded. Once retrieved from the instruction cache, the instruction bit is shifted down the pipe, so that simple combinational logic at each stage of the pipe can generate control signals for the data directly from the instruction bit. As a result, very little decoding is carried out in what is traditionally called the decode stage. The consequence of this lack of decoding means that more instruction bits must be used to determine what instructions should be done (and also, what should not be done), and which leaves fewer bits for things such as index registers.
  • All MIPS, SPARC, and DLX instructions have at most two register registers. During the decode stage, the two register names are identified in the instructions, and the two registers mentioned are read from the register file. In the MIPS design, the register file has 32 entries.
  • At the same time the register file is read, the logic of the instruction problem at this stage is determined if the pipeline is ready to carry out instructions at this stage. Otherwise, the logic of the problem will cause the Instruction Fetch and Decode stages to stop. In the kiosk cycle, these steps will prevent the initial flip-flops from receiving new bits.
  • If the translated instruction is a branch or jump, the address of the branch or jump target is calculated in parallel by reading the register file. The branch condition is calculated after the register file is read, and if the branch is taken or if the instruction is a jump, the PC predictor in the first stage is given the branch target, not the added PC that has been calculated. Some architectures utilize the ALU at the Execute stage, with the cost of instruction throughput decreasing slightly.
  • The decode stage ends with a fair amount of hardware: MIPS has the possibility of branching if the two registers are equal, so the 32-bit AND-wide tree runs in series after the register file is read, making a very long critical path through this stage. Also, branch target calculations generally require an additional 16 bits and an increase of 14 bits. Completing a branch in the decoded stage allows for only a single branch wrong-cycle branch penalty . Because branches are very often taken (and thus wrongly guessed), it is very important to keep this penalty low.

3. Execute / execute instructions or count addresses (execute)

  • The Execute Stage is where the actual calculation takes place. Usually this stage consists of the Arithmetic and Logic Unit, and also a few shifter. It can also include multipliers and double cycle dividers.
  • The Arithmetic and Logic Unit is responsible for carrying out boolean operations (and, or, not, nand, or, xor, xnor) and also for adding and subtracting integers. In addition to the results, ALU usually provides status bits such as whether the result is 0 or not, or if an overflow occurs.
  • Bit shifters are responsible for shifting and rotation.
  • The instructions for this simple RISC machine can be divided into three latency classes according to the type of operation:
  • Register operations (single cycle latency): Add, subtract, compare and logical operations. During the execution phase, two arguments are fed to a simple ALU, which results in the end of the execution stage.
  • Memory Reference (Two-cycle latency). All loaded from memory. During the execution phase, the ALU adds two arguments (registers and constant offsets) to produce a virtual address at the end of the cycle.
  • Multi-Cycle Instructions (Many cycle latencies). Duplicate integers and divide and all floating-point operations. During the execution phase, the operands for this operation are fed to multiply / split multi-cycle units. The rest of the pipeline is free to continue execution while the copying / distribution unit does its work. To avoid the complexity of the rewriting stage and issuing logic, multi-bicycle instructions write their results to a separate set of registers.

4. Access operands in data memory (memory access)

  • If data memory needs to be accessed , it is done at this stage.
  • During this stage, the results of the single cycle latency instruction are forwarded to the next stage. This forwarding ensures that one and two cycle instructions always write their results in the same stage of the pipe so that only one write port to the register file can be used, and is always available.
  • For caching data that is mapped directly and virtually marked, by far the simplest of many data caching organizations, two SRAMs are used, one saves data and the other stores tags.

5. Write the results in the register (writeback)

During this stage, both single cycle instructions and two cycles write the results to the register file.

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