Intel 80486.

Intel i486 (often called 486 or 80486) is a series of 32-bit Intel scalar CISC micro processors that are part of the Intel x86 processor family. i486 is the successor to the processor Intel 80386, processor micro 486 first time introduced in the 1989. The i486 is often called without additional prefix 80, for regulation court banned the figures used as they trade (such as 80486). Naming for this processor that is based on the number then totally removed simultaneously with marketed successor i486, which is the processor Pentium.

From the assessment device software, the instruction set of the family i486 is very similar to its predecessor, the Intel 80386, with some bit instructions extra.

From the ratings the device hardware, the architecture of the i486 is the progress of major. The processor’s own instruction and data caches are incorporated in a chip, a floating-point unit (FPU) additional on chip (special models DX), and a bus interface unit which improved its ability. As an extra, the conditions optimal, core processor can maintain the speed of execution of one instruction per clock cycle. Repair This is a rough doubling the performance of the Intel 80386 in clock rate the same. Even so, some i486 models turned out to be slower than the fastest 386 processor, specifically the ‘SX’ i486.

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Intel 80486 Architecture.

The initial model, 80486DX, was introduced with the 25 and 33 MHz models. Then the 50 MHz part was added, then DX2 / 50 doubled and DX2 / 66 parts, and then still, DX4 / 75 tripled and DX4 / 100 tripled.

The 486DX is then equipped with the cheaper 80486SX, which is also available in 16 and 20 MHz variants. The designations “SX” and “DX” match those of the 80386DX and 80386SX, but have different meanings. For 486, the SX designation indicates there is no FPU / Floating Point Unit on the chip. At the beginning of the 486SX unit, FPU was present but was deactivated; The model is then completely removed. An additional 80487DX upgrade chip is also offered, but this is not FPU; that is the whole, complete 80486 replacement processor that disables the original SX section.

A 50 MHz 80486 executes about 40 million instructions per second on average and is capable of achieving peak performance of 50 MIPS.

Pipeline On Intel 80486

The processor instruction use in pipeline

There are 5 stages of pipeline on Intel 80486, namely:

  1. Fetch
  • From cache or external memory
  • Use one of the two prefetch buffers, each measuring 16 bytes
  • Fill the buffer with new data as soon as the old data is finished using
  • On average it can take 5 instructions for one operation
  • Be independent of other stages so that the buffer can remain full

2. Decode stage 1

  • Opcode information and memory tracking mode
  • At most take the first 3 bytes of an instruction
  • Delegate to Decode stage 2 to retrieve the remaining instructions

3. Decode stage 2

  • Develop o- mode into control signal
  • Calculations for complex addressing modes

4. Execute

  • Operations on the ALU
  • Access cache
  • Perform an update to the register

5. Writeback

  • Updating many registers and fla g
  • Results are sent to the cache and the bus write interface is buffered

Intel Pentium

Archotecture of intel pentium

In the processor there is a set of registers that function as the memory level above the main memory and the cache in the hierarchy/register in the processor performs two roles.

  1. User Visible register: register whose contents can be known by the programmer, this register can also minimize references to main memory.
  2. Control and Status registers: registers used by CU, CPU operation controls and by the operating system to control program execution.

Register organization on Intel Pentium

The Register Set on the Pentium is to hold temporary results and control the execution of programs / instructions EAX, ECX, ED X, EBX, ESP, EBP, ESI, or EDI.

  • The 32-bit registers are named with the prefix E, EAX, etc., and at least 16 bits 0-15 from this register can be accessed with names like AX, SI.
  • Likewise, the eight lower bits (0-7) can be accessed with names like AL ​​& BL.
  • Comparison of flags available in 16-bit and 32-bit microprocessors can provide some clues related to the capabilities of this processor.
  • All of these flag registers include 6 flags related to data conditions (signs, zeros, carry, auxiliary, carry, overflow, and parity) and three flags related to machine operation, intrusion, Single-step and Strings).
  • Comparison of flags available in 16-bit and 32-bit microprocessors can provide some clues related to the capabilities of this processor.
  • All of these flag registers include 6 flags related to data conditions (signs, zeros, carry, auxiliary, carry, overflow, and parity) and three flags related to machine operation, interception , Single-step and Strings).
  • The EAP pointer instructions, known as program counter (PC) in an 8-bit microprocessor, are 32-bit registers to handle 32-bit memory addresses, and lower 16-bit IP segments are used for 16-bit memory addresses.
  • The register flag is a 32-bit register, but 14-bits are currently used for 13 different tasks .
  • I / O privileges use two bits in protected mode to determine which I / O instructions can be used, and nested tasks are used to show links between two tasks. • Processors also include control registers and system address registers, debug and test registers for system operation and debugging.

Interrupt processing on Intel Pentium

On the Pentium processor there are a number of interruptions and ways of processing / managing these interruptions.

  1. IN TR – Maskable Intterupt (Input)
  • Indicates that there are external e interruptions that have been generated.
  • If the IF (Interrupt Enable Flag) bit in the EFLAGS register is set, the Pentium processor generates 2 locked interrupts to acknowledge the cycle on the bus (to get the number type) and vector to an interrupt handler after the instruction being executed has been executed.

2. NMI – Non-Masable Intterupt (Input)

  • Indicates that a non-maskable interrupt external can degenerate.
  • The Pentium processor will vector the type 2 interrupt handler after the instruction being executed has been executed.
Vector pentium table with interrupts and exception
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