A.     Computer Input & Output Unit

     I / O module is a hardware interface ( interface ) to the system bus or central switch and controls one or more peripheral devices. The I / O module is not just a connecting module , but a device that contains logic in performing the communication function between peripherals and the computer bus. 

There are several reasons why devices are not directly connected to the computer system bus, namely:

  • The various methods of operating peripheral devices, so it is not practical if the computer system must handle various kinds of peripheral device operating systems.
  • The data transfer rate of peripheral devices is generally slower than the data transfer rate on the CPU or memory.
  • The data format and length of data on peripheral devices are often different from the CPU , so modules need to be synchronized.

For some of the reasons above, the I / O module has two main functions, namely:

a. As an interface device to the CPU and memory through the system bus.       

b. As an interface device with other peripheral equipment using certain data links .      

How the I / O module can carry out its work, namely bridging the CPU and memory with the outside world is the most important thing for us to know. The core of studying a computer’s I / O system is knowing the function and structure of the I / O module. Take a look at Figure 1, which presents the generic model of the module 

I / O.

  1. Function of I / O Module

I / O module is a component in a computer system that is responsible for controlling an external device or more and is also responsible for exchanging data between that external device with main memory or with CPU registers. In realizing this, an internal interface with the computer (CPU and main memory) is required and an interface with its external devices to carry out control functions.

The function in carrying out the tasks for the I / O module can be divided into several categories, namely:

• Control and timing.

• CPU communication.

• Communication of external devices.

• Data buffering.

• Error detection.

Control and timing functions ( control & timing ) are important to synchronize the work of each computer component. At one time the CPU communicates with one or more devices with erratic patterns and the speed of transfer of data communication varies, both with internal devices such as registers, main memory, secondary memory, peripheral devices. The process can run if there are control and timing functions that govern the system as a whole. Examples of controls for transferring data from peripherals to the CPU via an I / O module can include the following steps :

  1. Request and check device status from CPU to I / O module.
  2. The I / O module provides answers to CPU requests.
  3. When an external device is ready for data transfer, the CPU will send commands to the I / O module.
  4. The I / O module will receive data packets of a certain length from the peripherals.
  5. Then the data is sent to the CPU after synchronizing the data length and the transfer speed by the I / O module so that the data packets can be received by the CPU properly.
  6. Data transfer will not be separated from the use of the bus system, so the CPU and I / O module interaction will involve the control and timing of a bus arbitration or more. The communication function between the CPU and the I / O module includes the following processes:
  7. Command Decoding , i / O module receives commands from the CPU that are sent as signals to the control bus. For example, an I / O module for disks can receive commands: Read sector, Scan record ID, Format disk.
  8.  Data , the exchange of data between the CPU and I / O modules via the data bus. 
  9.  Status Reporting i.e. reporting the status of I / O module status and peripheral devices, generally in the form of Busy or Ready status . Also the status of wide – range fault condition ( error ).    
  10. Address Recognition that the equipment or components making up a computer can be contacted or called must have a unique address, as well as on peripheral devices, so that each I / O module must know the address of the controlled peripheral.  
  11. On the side of the I / O module to the peripheral device there is also communication which includes data communication, control and status.

The next function is buffering . The main purpose of buffering is to get data adjustments due to differences in the rate of data transfer from peripheral devices to the processing speed on the CPU. Generally the rate of data transfer from peripheral devices is slower than the speed of the CPU or storage media. The last function is error detection. If there are problems with the peripheral device so the process cannot be run, the I / O module will report the error. For example error information on printer peripherals such as: curled paper, out of ink, out of paper, and so on. A common technique for error detection is the use of parity bits.   

  1. I / O Module Structure

There are various kinds of I / O modules as the computer itself develops, a simple and flexible example is the Intel 8255A which is often called the PPI ( Programmable Peripheral Interface ). However the complexity of an I / O module, there are structural similarities

I / O module interface to the CPU via the computer system bus there are three channels, namely data channel, address channel and control channel. The most important part is the I / O logic block that is associated with all peripheral interface equipment, there are settings and switching functions in this block.

  1. Input / Output Techniques

There are three techniques in I / O operations, namely: Programmed I / O, interrupt-driven I / O, and DMA ( Direct Memory Access ). All three have advantages and drawbacks, the use is adjusted according to the un t uk work each – each technique.  

In programmed I / O, data is exchanged between the CPU and I / O modules. The CPU executes programs that provide CPU I / O operations directly, such as moving data, sending read and write commands, and monitoring devices. The weakness of this technique is that the CPU will wait until the I / O operation is complete, making the I / O module waste time, especially since the CPU is operating faster. In this technique, the I / O module cannot interrupt the CPU of the processes that are instructed on it. The entire process is the responsibility of the CPU until the complete operation is carried out.

To carry out I / O commands, the CPU will issue an address for the I / O module and its peripheral devices so that it is specifically specified and an I / O command to be performed. There are four classifications of I / O commands, namely:

a. Control command .        

This command is used to activate the peripheral device and notify the task that was ordered to him.

b. Test command .        

This command is used by the CPU to test various I / O module status conditions and peripherals. The CPU needs to know the peripherals are active and ready to use, also to find out the I / O operations that are performed and detect errors.

c. The read command .        

The command in the I / O module is to take a data packet and then place it in the internal buffer. The next process the data packet is sent via the data bus after data synchronization and transfer speed occur.

d. Write command .        

This command is the opposite of read . The CPU instructs the I / O module to retrieve data from the data bus to be given to the peripheral device for which the data is intended. 

In engineering I / O programmed, there are two kinds inplementasi I / O command that is stated in the instruction I / O, namely: memory-mapped I / O and isolated I / O   

In memory-mapped I / O , there is a single space for memory location and I / O devices. The CPU treats the status registers and I / O module data registers as memory locations and uses the same machine instructions to access both memory and I / O devices. The consequence is that a single channel is required for reading and a single channel for writing. The advantage of memory-mapped I / O is programming efficiency, but it takes up a lot of address memory space.    

In the isolated I / O technique , there is a separation of the addressing space for memory and the addressing space for I / O. This technique requires a bus equipped with a memory reading and writing channel plus an output command channel. The advantage of isolated I / O is the lack of I / O instructions   

The interrupt-driven I / O technique allows the process to not waste time. The process is that the CPU issues the I / O command on the I / O module, while the I / O command is executed by the I / O module, the CPU will execute other commands. If the I / O module has finished executing the instructions given to it, it will interrupt the CPU that the task has been completed.

In this technique command control is still the responsibility of the CPU, both taking commands from memory and executing the contents of those commands. There is a step forward from the previous technique, the CPU multitasking several commands at once so that there is no waiting time for the CPU.  

The way the interrupt technique works on the side of the I / O module is that the I / O module accepts commands, for example read . Then the I / O module executes a reading command from the peripheral and puts the data packet into the I / O module data register, then the module issues an interrupt signal to the CPU via the control channel. Then the module waits for the CPU’s requested data. When a request occurs, the module places data on the data bus and the module is ready to receive further commands. 

  1. P engolahan current interrupt device I / O has completed an I / O operation is as follows: Device I / O will send an interrupt signal to the CPU.
  2. The CPU completes the operation it is running then responds to interruptions.
  3. The CPU checks the interrupt, if it is valid then the CPU will send an acknowledgment signal to the I / O device to stop the interruption.  
  4. The CPU prepares controlling transfers to interrupt routine. The thing to do is to save the information needed to continue the operation that was carried out before the interruption. The information needed is in the form of:
  5. Processor status, contains a register called PSW ( status word program ).
  6. The location of the next instruction to be executed. The information is then stored in the system controller stack.
  7. Then the CPU will save the executable PC ( program counter ) before interruption to the controller stack along with PSW information. Next prepare the PC for handling interruptions.
  8. Then the CPU processes the finished interrupt.
  9. If interrupt processing is complete, the CPU will recall information that has been stored on the controller stack to continue operations before the interruption. There are various techniques that the CPU uses in handling this interrupt program, including:

Multiple Interrupt Lines Software polls Daisy Chain Arbitration buses   

The simplest technique is to use an interrupt line with numerous ( Multiple Interrupt Lines ) between the CPU and modules – I / O modules. But it is not practical to use a number of bus lines or CPU pins to all interrupt channels of I / O modules.

Another alternative is to use poll software . The process, if the CPU is aware of an interruption, then the CPU will go to the interrupt service routine whose job is to poll all the I / O modules to determine the module that is interrupting.  

The disadvantage of software polls is that it takes a long time because they have to identify all modules to find out which I / O modules are interrupting.  

A more efficient technique is daisy chain , which uses hardware polls . All I / O modules are connected in a CPU interrupt channel in a chain . If there is an interrupt request, the CPU will run an acknowledgment signal that runs on the interrupt channel until it encounters the I / O module that sends the interrupt.    

The next technique is bus arbitration . In this method, the I / O module first gets the bus control before this module uses the interrupt request channel. Thus there will only be an I / O module that can interrupt. 

Ø   Direct Memory Access (DMA)

The technique described earlier, programmed I / O and Interrupt-Driven I / O has a weakness, namely the process that occurs in the I / O module still involves the CPU directly. This has implications for:

· The I / O transfer rate depends on the CPU operating speed.         

· CPU work is interrupted due to direct interruptions.         

Starting from the weaknesses above, moreover to handle large-volume data transfer developed a better technique, known as Direct Memory Access (DMA).  

The working principle of DMA is that the CPU will delegate the work of I / O to the DMA, the CPU will only be involved at the beginning of the process to give complete instructions on the DMA and the end of the process. Thus the CPU can run other processes without much interference with interruptions .

In carrying out data transfers independently, DMA requires the transfer of bus control from the CPU. For this reason DMA will use the bus if the CPU does not use it or DMA forces the CPU to temporarily stop using the bus. The last technique is more commonly used, often called cycle stealing , because the DMA module takes over the bus cycle. 

Temporarily stopping the use of the bus is not a form of interruption, but only a temporary termination of the process that has implications only for CPU execution delays.

Ø   External Devices

A computer machine will have value if it can interact with the outside world. More than that, a computer will not function if it cannot interact with the outside world. Take for example, how can we instruct the CPU to perform an operation when there is no keyboard. How do we see the work of a computer system when there is no monitor. Keyboard and monitor are located in the computer’s external device. External devices, or more commonly called peripherals, are connected in the CPU system through its controller hardware, the I / O module as explained earlier.  

In general, external devices are classified into 3 categories:

  1. Human Readable , which is a device related to humans as computer users. For example: monitor, keyboard, mouse, printer, joystick, disk drive.
  2. Machine readable , which is a device related to equipment. Usually in the form of sensor and transducer modules for monitoring and control of an equipment or system.
  3. Communication , which is a device related to long distance communication. For example: NIC and modem.

Classification can also be based on the direction of the data, namely the output device, input device and output-input combination. Examples of output devices: monitors, projectors and printers. Input devices such as: keyboard, mouse, joystick, scanner, mark reader, bar code reader. One of the basic features of a computer is its ability to exchange data with other devices. This communication capability allows a human operator, for example , ntuk using the keyboard and the display layer to process text and graphics. Humans develop the use of computers to communicate with other computers through the internet and access information throughout the world. In other applications, computers are not as obvious but are equally important. Computers become an integral part of household appliances, manufacturing equipment, transportation systems, banking and point-of-sale terminals. In such applications, input to a computer can come from sensor switches, digital cameras, microphones, or fire alarms. The output can be a sound signal sent to the speaker or a digitally coded command to change the motor speed, open the valve, or cause a robot to move in a certain way . In short, general-purpose computers must have the ability to exchange information with a number of devices in a variety of environments. 

The setting is simple to connect the I / O device to a computer is to use a single bus arrangement , Bus that clicking E nable all devices connected to it to exchange information. Usually, the arrangement consists of three sets of paths used to carry addresses, data, and control signals. Each I / O device is assigned a unique set of addresses. When the processor places an address on the address line, devices that recognize this address respond to commands stated on the control line. The processor requests read or write operations, and the requested data is transferred through the data path. At the time the device I / O and memory address space to share the same , the setting is called memory-mapped I / O.  

With memory mapped I / O, each machine instruction that can access memory can be used to transfer data to or from I / O devices.

Most computer systems use memory mapped I / O. Some processors have special In and Out instructions for running I / O transfers. For example, processors in the Intel family have special I / O instructions and separate 16bit address spaces for I / O devices. When building a computer system based on this processor, designers have the choice of connecting I / O by using a special I / O address space or simply by combining it as part of the memory address space. The most recent approach is by far the most common because it involves

the use of simpler software. One of the benefits of separate address spaces is that I / O devices handle fewer address lines. Note that a separate I / O address does not have to mean that the I / O address path is physically separate from the I / O address path physically separated from the memory address path. A special signal on the bus indicates that the requested read or write transfer is an I / O operation. When this signal is declared, the memory unit ignores the requested transfer.

The I / O device analyzes the address bus loworder bit to determine whether it should respond. Mengenable address decoder device to recognize the address at the time of this address appears on track to save the data alamat.Register data transferred ked al A m of the processor. The status register contains information that is relevant to the operation of the I / O device. Data registers and statuses are linked to the data bus and are assigned unique addresses. Address decoders, data registers and status, and control circuits needed to coordinate the transfer of I / O to form a device interface circuit.   

I / O devices operate at speeds very different from the processor. When human operators enter characters on the keyboard, the processor is able to execute millions of instructions between sequential character entries.

An instruction that reads a character from the keyboard should only be executed when the character is available in the keyboard interface input buffer. Also we must ensure that the input character is only read once.


In carrying out the storage function, semiconductor memory may experience errors. Both serious errors are usually a physical damage to memory and minor errors related to data stored. Minor errors can be corrected again. To make a mistake correction of the stored data, two mechanisms are needed, namely the error detection mechanism and the error repair mechanism.

The error detection mechanism is by adding data word (D) to a code, usually a parity check bit (C). So the stored data has a length of D + C. Errors will be known by analyzing the data and the parity bit. The simplest error repair mechanism is the Hamming code. This method was invented by Richard Hamming at Bell Lab in 1950.

To reduce or even eliminate binary password errors, you can also use the Hamming method.

  1. Binary Password Error Control

Many different ways to control binary password errors, including the way “Hamming”, “Block Coding” and so on. In this case, one method of controlling errors for single digit errors is discussed with the Hamming method, which is the H matrix for tracking password errors received. Digital passwords sent as pulse numbers “0” and numbers “1” in order to correct errors that might occur at the recipient need to be encrypted again using the Hamming method. A matrix Ħ is selected which produces HT = 0, where T is a vector whose elements are digital codes to be sent. Matrix H consists of r diagonal matrix columns and n arbitrary matrix columns, where n is the number of digital digits to be sent. On receiving or parachuting aircraft, the received signal, for example as a vector R, is multiplied again by the matrix H and produces S syndrome. If S = HR = 0, it means that the signal received is correct or matches the signal sent. But if S = HR ≠ 0, it means that the signal received is an error. Errors that occur can be seen from the signs of the syndrome that is formed. Matching syndromic cues with matrix H will find out which errors occur in which number. For example, if the syndrome signal matches column 5, then an error occurred at number 5 of the message being sent.

  • Example tracking error

 A message is sent by the recipient of the message received as a password 101111111. To see whether this message is correct or not, the message received must be checked. To check the received password, you need to look for the syndrome signal, which is the multiplication of the matrix H with the password received. The results of the multiplication are as follows:

The syndromic signal obtained from the above calculation is [1 0 1 0] -1. If this syndromic signal is matched with matrix H, it appears that the syndromic signal matches column 2. Thus, an error occurs at number 2, ie from the number “0” must be changed to number “1”.

2. Error correction    

The error detection mechanism is by adding data word (D) to a code, usually a parity check bit (C). So the stored data has a length of D + C. Errors will be known by analyzing the data and the parity bit. The simplest error repair mechanism is the Hamming code.

The error correction mechanism will increase reliability for memory but the risk is adding complexity to data processing. Besides that the error correction mechanism will increase memory capacity due to the addition of parity check bits. So the memory size will be several percent larger or in other words the storage capacity will be reduced because some locations are used for error correction mechanisms.

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