The information involved in any operation performed by the CPU needs to be addressed. In computer terminology, such information is called the operand. Therefore, any instruction issued by the processor must carry at least two types of information. These are the operation to be performed, encoded in what is called the op-code field, and the address information of the operand on which the operation is to be performed, encoded in what is called the address field.

Instructions can be classified based on the number of operands as three-addresstwo-addressone-and-half-addressone-address, and zero-address. We explain these classes together with simple examples in the following paragraphs. It should be noted that in presenting these examples, we would use the convention operationsourcedestination to express any instruction. In that convention, operation represents the operation to be performed, for example, addsubtractwrite, or read. The source field represents the source operand(s). The source operand can be a constant, a value stored in a register, or a value stored in the memory. The destination field represents the place where the result of the operation is to be stored, for example, a register or a memory location.

A three-address instruction takes the form operation add-1add-2add-3. In this form, each of add-1add-2, and add-3 refers to a register or a memory location. Consider, for example, the instruction ADD R1, R2, R3. This instruction indicates that

the operation to be performed also. It also indicates that the values to be added are those stored in registers R1 and R2 that the results should be stored in register R3. An example of a three-address instruction that refers to memory locations may take the form ADD A, B, C. The instruction adds the contents of memory location to the contents of memory location and stores the result in memory location C.

A two-address instruction takes the form operation add-1add-2. In this form, each of add-1 and add-2 refers to a register or a memory location. Consider, for example, the instruction ADD R1, R2. This instruction adds the contents of register R1 to the contents of register R2 and stores the results in register R2. The original contents of register R2 are lost due to this operation while the original contents of register R1 remain intact. This instruction is equivalent to a three-address instruction of the form ADD R1, R2, R2. A similar instruction that uses memory locations instead of registers can take the form ADD A, B. In this case, the contents of memory location are added to the contents of memory location and the result is used to override the original contents of memory location B.

The operation performed by the three-address instruction ADD A, B, C can be performed by the two two-address instructions MOVE B, C and ADD A, C. This is because the first instruction moves the contents of location into location and the second instruction adds the contents of location to those of location (the contents of location B) and stores the result in location C.

A one-address instruction takes the form ADD R1. In this case, the instruction implicitly refers to a register, called the Accumulator Racc, such that the contents of the accumulator are added to the contents of the register R1 and the results are stored back into the accumulator Race. If a memory location is used instead of a register then an instruction of the form ADD B is used. In this case, the instruction adds the content of the accumulator Race to the content of memory location and stores the result back into the accumulator Race. The instruction ADD R1 is equivalent to the three-address instruction ADD R1, Racc, Racc or to the two-address instruction ADD R1, Racc.

Between the two- and the one-address instruction, there can be a one-and-half address instruction. Consider, for example, the instruction ADD B, R1. In this case, the instruction adds the contents of register R1 to the contents of memory location and stores the result in register R1. Because the instruction uses two types of addressing, that is, a register and a memory location, it is called a one-and-half-address instruction. This is because register addressing needs a smaller number of bits than those needed by memory addressing.

It is interesting to indicate that there exist zero-address instructions. These are the instructions that use stack operation. A stack is a data organization mechanism in which the last data item stored is the first data item retrieved. Two specific operations can be performed on a stack. These are the push and pop operations. 

As can be seen, a specific register, called the stack pointer (SP), is used to indicate the stack location that can be addressed. In the stack push operation, the SP value is used to indicate the location (called the top of the stack) in which the value (5A) is to be stored (in this case it is location 1023). After storing (pushing) this value the SP is

incremented to indicate to location 1024. In the stack pop operation, the SP is first decremented to become 1021. The value stored at this location (DD in this case) is retrieved (popped out) and stored in the shown register.

Different operations can be performed using the stack structure. Consider, for example, an instruction such as ADD (SP), (SP). The instruction adds the contents of the stack location pointed to by the SP to those pointed to by the SP 1 and stores the result on the stack in the location pointed to by the current value of the SP. The different ways in which operands can be addressed are called the addressing modes. Addressing modes differ in the way the address information of operands is specified. The simplest addressing mode is to include the operand itself in the instruction, that is, no address information is needed. This is called immediate addressing. A more involved addressing mode is to compute the address of the operand by adding a constant value to the content of a register. This is called indexed addressing. Between these two addressing modes there exist several other addressing modes including absolute addressing, direct addressing, and indirect addressing. Several different addressing modes are explained below.

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